Logic Gates, Logic Circuits & Boolean Algebra

Introduction To Logic Gates Basic Definitions

 Logic Gates:

Logic gates are the building blocks in digital circuits, perform simple logical operations on one or more output and produce a single output. With the help of connecting different logic gates, we can perform arithmetic and other logical operations within seconds.


  • AND, OR, and NOT are basic logic gates

  • Input and output are binary numbers

  • The state of an input and output terminal often changes. That is it can change from 1 to 0 or vice versa. This is because the circuit processes the data and the state of the terminal changes accordingly

  • There are many ways to implement logic gates like RTL (resistor transistor logic), DTL (diode transistor logic), TTL (transistor-transistor logic) and the most contemporary logic CMOS logic

Boolean Algebra:

It is the branch of algebra in which the variable values are true (binary 1) or false (binary 0). 

We need to learn Boolean algebra because it simplifies the solution of logical problems. It also simplifies the design of logic circuits. According to the laws of Boolean algebra, there are seven logical operations which are stated below.


  1.  Buffer

  2. NOT  

  3. AND (.)

  4. OR (+)

  5. NOR

  6. NAND

  7. XOR (⊕)

  8. XNOR


Whereas, NOT, AND and OR are three basic Boolean algebra operators. Boolean expressions use these operators and produce output that is either true or false.

Logic Symbol:

A logic symbol is a graphical representation of elements in electronics. For each logic gate, there is a unique logic symbol. These symbols help to identify one component to another. For complex logic gates, we replace multiple gates with a single rectangular shape box. Inputs are on the left side while outputs are on the right. Some symbols are with bubbles and the rest of them are without bubbles. Some Boolean operators are inverse of each other. The bubble helps to identify them. For example, an AND gate has no bubble while its counterpart NAND has a bubble at the output side. 


Figure 1: Logic gates and schematic symbols

Logic Function Or Logic Expression:

It is a mathematical depiction of a logic circuit. It provides the functionality of output in terms of input. The expression contains input and output variables along with Boolean operators ( . , + , ⊕). In the expressions below, Y is output, while A and B are two inputs.


Y = A.B

Y = A + B

Y = A ⊕ B

Y = (A.B) ⊕ C


Logic expressions may contain more than one Boolean operator.

Logic Waveform Or Timing Diagram:

It is a graphical representation of the inputs and outputs of a logic circuit with respect to time. We can observe logic waveforms using an oscilloscope.


In the timing diagram, the x-axis shows the time while the y-axis represents the digital voltage levels. To analyze and examine digital systems, wave shapes are important. Some important wave parameters are discussed in this article. The figure below shows the AND gate timing diagram. You can easily understand the logic of examining this diagram. The output goes high only when both inputs are high.



Timing diagram
Figure 2: AND gate timing diagram


Polarity Indicator | Positive & Negative Logic:

The digital systems use both positive and negative logic depending upon the requirement. I have written on logic levels in my previous article. Positive logic means HIGH voltage represents binary 1 (ON state) while LOW voltage represents binary 0 (OFF state). Negative logic means LOW voltage represents binary 1 (ON state) while HIGH voltage represents binary 0 (OFF state). The figure below shows the positive and the negative logic of NAND gates. The bubbles or circles at the input side show the negative logic. 



Figure 3: Positive and negative logic NAND gate

Truth Table:

A truth table curated all possible inputs and the corresponding output produced by a logic gate. All the logic gates can produce a single output (either 1 or 0). So the table contains multiple input columns (the number of columns is equal to the number of inputs) and a single output column. Each row contains possible input combinations and corresponding output produced by that combination. The logic expression or Boolean expression helps to evaluate the output of the logic system. With the help of a truth table, we can understand the operation of logic gates. To analyze the operation of any gate we need to go through its truth table. It is an invaluable tool in digital circuit designing. For example, in the table below, the truth table of a 2 input AND gate is given. The number of inputs is two and possible input combinations are 4. The logic system with n-inputs, the truth table will have 2n possible input combinations. Input codes are always in ascending order.


2 Input AND Gate

Input A

Input B

Output

0

0

0

1

0

0

0

1

0

1

1

1



Examples:

Evaluate the number of possible input combinations for a 4-input gate.


Number of inputs = n = 4

Number of possible input combinations = 2n = 24 = 16


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Collector Feedback Bias - AC | DC Load Line & Q Point Calculations

<title>Collector Feedback Bias - AC | DC Load Line And Q Point

Collector Feedback Bias - AC | DC Load Line & Q Point Calculations


Learning Objectives:
  • What is collector feedback bias?
  • Evaluate Q point, AC load line, DC load line
  • How to select Q point according to the application?
    • Centred Q point
    • Q point near saturation
    • Q point near the cutoff 
  • Maximum possible peak to peak voltage

This topic helps you to design collector feedback bias circuits.

This is another biasing technique of BJT based circuits. In this technique, a resistor is connected in between base and collector terminals. The collector terminal provides biasing voltage for the base emitter terminal. 
There are a similar number of components required as it is in base bias. But it is far more stable than the base bias circuit. The circuit has better stability that is thermal or bias stability. 
The important aspect of this bias is that it is designed to work only in the active region.
Collector feedback bias
Fig 1: A Collector feedback bias

DC Load Line:

KVL at the output circuit.
-VCC + ICRC + IBRC + VCE = 0 ..eq 1
IB = IC/β
Substitute IB, equation 1 becomes
-VCC + ICRC + (IC/β)*RC + VCE = 0
-VCC + ICRC (1+ 1/β) + VCE = 0..eq2

Substitute VCE = 0 in ..eq2
VCC = ICRC(1+1/β)
IC = VCC/RC(1+1/β)
With the help of approximation 1+1/β = 1
IC = VCC/RC ..eq3

Substitute IC = 0 in ..eq2
VCE = VCC ..eq4

Q Point (VCEQ , ICQ):

Apply KVL to the input circuit.
-VCC + ICRC + IBRB + VBE = 0 ..eq5
IB = IC/β
Substitute IB and solve for IC
-VCC + ICRC + ICRB/β+ VBE = 0
-VCC + IC(RC + RB/β)+ VBE = 0
ICQ = (VCC - VBE) / (RC + RB/β)..eq6

KVL at output circuit.  
-VCC + ICRC + IBRC + VCE = 0 ..eq7
IB = IC/β
Substitute IB and solve for VCE
VCE = VCC - ICRC - ICRC/β
VCE = VCC - ICRC(1+ 1/β)
1+1/β ~ 1
VCEQ = VCC - ICRC..eq8

AC Load Line:

I am not going into the details of AC load line. 
iC(sat) = ICQ + VCEQ/rC..eq9
vce(cut) = VCEQ + ICQ*rC..eq10

Example 1: RB = 40k


Step 1: DC Load Line
From eq3 and eq4
VCE = 10V
IC = 10mA

Step 2: Q Point (VCEQ , ICQ)

From eq6
ICQ = (VCC - VBE) / (RC + RB/β)
ICQ = (10 - 0.7) / (1k + 40k/100)
ICQ = 6.6mA

From eq8
VCEQ = VCC - ICRC
VCEQ = 10 - 6.6m*1k
VCEQ = 3.4V

Step 3: AC Load Line
From eq9
iC(sat) = ICQ + VCEQ/rC
iC(sat) = 6.6m + 3.4/500
iC(sat) = 6.6m + 6.8m
iC(sat) = 13.4mA

From eq10
vce(cut) = VCEQ + ICQ*rC
vce(cut) = 3.4 + 6.6m*500
vce(cut) = 6.7V

Step 4: Maximum Peak To Peak Voltage:
It is also called output compliance. I discussed it in detail in base bias analysis.

We will check for both compliances. Amplifier compliance will be the smaller value.
PP =2* VCEQ = 6.8V
PP = 2*ICQ*rC = 6.6V

Since the Q point is almost in the middle of the AC load line. Hence both compliances are almost the same. It is also visible in the figure below

AC | DC load line collector feedback bias
Fig 2: Example 1

Example 2: RB = 100k


Step 1: DC Load Line
From eq3 and eq4
VCE = 10V
IC = 10mA

Step 2: Q Point (VCEQ , ICQ)

From eq6
ICQ = (VCC - VBE) / (RC + RB/β)
ICQ = (10 - 0.7) / (1k + 100k/100)
ICQ = 4.65mA

From eq8
VCEQ = VCC - ICRC
VCEQ = 10 - 4.65m*1k
VCEQ = 5.35V

Step 3: AC Load Line
From eq9
iC(sat) = ICQ + VCEQ/rC
iC(sat) = 4.65m + 5.35/500
iC(sat) = 4.65m + 10.7m
iC(sat) = 15.35mA

From eq10
vce(cut) = VCEQ + ICQ*rC
vce(cut) = 5.35 + 4.65m*500
vce(cut) = 7.6V

Step 4: Maximum Peak To Peak Voltage:
We will check for both compliances. Amplifier compliance will be the smaller value.
PP =2* VCEQ = 10.7V
PP = 2*ICQ*rC = 4.65V

Output compliance is the smaller value and hence it is 4.65V. Or you can say maximum peak to peak voltage swing should not be greater than 4.65V.

Solved examples on collector feedback bias AC | DC load lines
Fig 3: Example 2

Example 3: RB = 150k


Step 1: DC Load Line
From eq3 and eq4
VCE = 10V
IC = 10mA

Step 2: Q Point (VCEQ , ICQ)

From eq6
ICQ = (VCC - VBE) / (RC + RB/β)
ICQ = (10 - 0.7) / (1k + 150k/100)
ICQ = 3.72mA

From eq8
VCEQ = VCC - ICRC
VCEQ = 10 - 3.72m*1k
VCEQ = 6.28V

Step 3: AC Load Line
From eq9
iC(sat) = ICQ + VCEQ/rC
iC(sat) = 3.72m + 6.28/500
iC(sat) = 3.72m + 12.56m
iC(sat) = 16.28mA

From eq10
vce(cut) = VCEQ + ICQ*rC
vce(cut) = 6.28 + 3.72m*500
vce(cut) = 8.14V

Step 4: Maximum Peak To Peak Voltage:
We will check for both compliances. Amplifier compliance will be the smaller value.
PP =2* VCEQ = 12.56V
PP = 2*ICQ*rC = 3.72V

Output compliance is the smaller value and hence it is 3.72V. Or you can say maximum peak to peak voltage swing should not be greater than 3.72V.

AC DC load lines calculations collector feedback bias
Fig 4: Example 3

Conclusion:

You have observed the different values of RB and Q point position on the load line. Q point remains in the active region for a wide range of RB. In collector feedback bias, as you decrease RB, the Q point shifts towards saturation but doesn't reach the saturation region.

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