Karnaugh Map solved examples (three, four and five variables K-Map)

 SOP and POS K Map Solved Examples:

In this tutorial, there are several solved examples of mapping the standard and non-standard POS and SOP expressions to the K-Map. I tried to make this as simple as possible. 

Mapping The Standard POS And SOP To The Karnaugh Map:

Example 1: Map the three variable SOP expression: \[\bar A \bar B \bar C+ A \bar B C + \bar ABC+AB \bar C\]

For three variables, the k map has 8 cells (4x2 or 2x4) grid.

No simplification is possible.

Example 2: Map the three variable standard SOP expression: \[\bar A \bar B \bar C+ \bar AB \bar C+AB \bar C\]

Another simple SOP expression is given. Directly map it.

The simplified expression is \[\bar A \bar C+B\bar C\]

Example 3: Map the POS expression: \[(A+B+C)(\bar A +\bar B + \bar C)(A +\bar B +C)\]

In this example, standard POS expression is a given. Map it directly.

The simplified expression is \[(A+C)(\bar A +\bar B + \bar C)\]

 Mapping The Non-standard POS And SOP To The Karnaugh Map: 

Mapping the non-standard terms needs some extra steps. There are some possibilities to make your work simple. Let's begin with some examples.

Example 4: Map the SOP expression: \[ \bar A + A \bar B + AB\bar C\]

First method: How to map a non-standard SOP expression into a K-map: 

The given expression has three SOP terms, and two of them are non-standard terms. The problem is how to map it. Draw the truth table, and then map the values to K-Map.

\[A\]	\[B\]	\[C\]	\[ \bar A + A \bar B + AB\bar C\]
0	0	0	1
0	0	1	1
0	1	0	1
0	1	1	1
1	0	0	1
1	0	1	1
1	1	0	1
1	1	1	0

Once we get the truth table, it is easy to map the values on the K-Map.

It is an interesting question. There are 3 groups, two of them are quad (4-cells) and one is a pair (2-cells).  All three groups are overlapping. We prefer overlapped groups because they will result in simpler and reduced expressions. 

The simplified expression is:

\[\bar A+ \bar B+B \bar C\]

Example 5: Map the SOP expression: \[ AB + A \bar B C+ ABC\]

There is a non-standard term. To map it on a K-map, there should be standard terms. The first method is to draw a truth table and get all the minterms from there as discussed in example 4. The second method is to find out all the terms by analyzing the given expression.

Second method: How to map a non-standard SOP expression into a K-map: 

The first step is to convert the non-standard SOP expression into a standard SOP. After getting the expression in a standard format, we will be able to map it in Karnaugh Map.

The simplified expression has two groups. These are pairs (2-cells in each group). The simplified SOP expression has two sum-of-product terms. In each term, there are only two variables.

 

Example 6: Draw K-Map for three variable non-standard SOP expression: \[ A + BC\]

In standard SOP form.

\[AB \bar C+ A \bar BC+A\bar B \bar C+ ABC+\bar ABC\]

After mapping, two groups are formed, a quad (4 cells) and a pair (2-cells). The simplified expression contains only two terms. 

\[ A + BC\]

Example 7: Map the four variable non-standard SOP expression: \[ A\bar B \bar C D + \bar ABC \bar D+B\bar C D+A C \bar D\]

In standard SOP form:

\[ A\bar B \bar C D + \bar ABC \bar D+AB\bar C D +\bar AB \bar CD+ABC \bar D +A \bar B C \bar D\]

For four variables, the K-map consists of 16-cells (4x4). 

After mapping, there are four groups of 2-cells. We get the simplified SOP expression. It has four terms each with three variables in it. Have a look at simplified expression.

\[B \bar C D+ A \bar C D+BC\bar D+AC \bar D\]

Example 8: Map four variable non-standard SOP logic expressions. \[ A\bar B + A\bar B \bar C  D+ C D+B \bar C D+ABCD\]

Transform in the standard SOP form. 

\[ A\bar B \bar C D + \bar ABC \bar D+AB\bar C D +\bar AB \bar CD+ABC \bar D +A \bar B C \bar D\]

Example 9: Map the four variable standard POS expression in a K map: \[ (A+\bar B+C+\bar D)(\bar A+B+\bar C+D)(\bar A+\bar B+\bar C+\bar D)\]

The standard POS expression is given, map it directly. While mapping the POS expression, write '0' instead of '1'. No further simplification is possible.

Example 10: Map the four variable non-standard POS expression in a Karnaugh Map: \[ (X+\bar Y)(\bar X+\bar Y+\bar Z)( W+\bar Z)(W+X+Y+Z)\]

The POS expression is in a non-standard form. The first step is to convert it into the standard POS and map it. If you don't want to convert in the non-standard form, just draw a truth table and pick out the input combinations that produce 'zeros' at the output. For POS expression, map zeros in the K-Map.

Example 11: Draw five variable Karnaugh Map from the following standard SOP expression: 

\[\bar A B \bar C D \bar E+\bar A \bar B \bar C DE+A\bar B \bar C DE+AB \bar C \bar D \bar E +\bar A BCD \bar E + \bar A BC\bar D E+\]\[ \bar A \bar B \bar C \bar D \bar E+ \bar A \bar B CDE+AB\bar C D \bar E+AB\bar C DE\]

For five variables, there are 25 = 32 cells. Instead of a single 32-cells K-Map, we use 2 16-cells K-Map. The expression is already in standard SOP format. Just carefully map it.

 

The simplified expression is:

\[\bar A \bar B \bar C \bar D \bar E + \bar A BC \bar D E + A B \bar C \bar D \bar E + \bar A \bar B DE + \bar A B D \bar E + AB \bar C D + A \bar C DE \]

DC Analysis BJT (Numericals, Design Problems) part 3

 This is another tutorial on BJT DC analysis. This tutorial is important from a design perspective. How to set circuit parameters, to work in an active mode, or in saturation mode or cut-off mode. For example, change in base and collector resistors (RC and RB) will result in changes in the base and collector currents. This change will have a direct impact on the operating mode of the transistor. The design problems are a little bit tricky. So, let's get started.

Example # 1: Calculate RB, RC and RE.

\[I_{CQ}=\frac{1}{2}I_{C(sat)}\]

\[I_{C(sat)}=8mA=4mA\]

\[V_C=18V\]

\[\beta=110\]

Apply KVL at the input loop.

\[-V_B+I_BR_B+V_{BE}+I_ER_E=0 \text {  equation 1}\]

\[I_C=\beta I_B\]

\[I_B=36\mu A\]

\[I_E =I_C+I_B\]

\[I_E=4.036mA\]

Calculate RC.

\[ R_C=\frac{V_{CC}-V_C}{I_{CQ}}\]

\[R_C=2.5k\Omega\]

 and RE set the Q point value and slope of the load line.

\[I_{C(sat)} = \frac{V_{CC}}{R_C+R_E}\]

\[R_C+R_E = \frac{28}{8m}=3.5k\Omega\]

\[ R_C = 3.5k-2.5k = 1k \Omega\]

Substitute RE in equation 1 and evaluate RB.

\[-28+36\mu R_B+0.7+4.036m*1k=0\]

\[R_B=646k\Omega\]

Example # 2: Calculate VCC, RC, RB

From load line,

\[V_{CC} = 20V\]

\[I_{C(sat)}=8mA\]

\[I_{BQ}=40 \mu A\]

\[I_{C(sat)}=\frac{V_{CC}}{R_C}\]

\[R_C=2.5k \Omega\]

For RB, apply KVL at the input loop.

\[-V_{CC}+I_B R_B+V_{BE}=0\]

\[-20+40 \mu R_B+0.7=0\]

\[R_B=482k \Omega \]

Example # 3: Design a common base NPN transistor with following parameters.

\[I_E=1.5mA\]

\[V_{CB} =7.5V\]

\[V_{CC}=15V\]

\[V_{CE}=-5V\]

Apply KVL at the input loop.

\[-V_{EE}+V_{BE}+I_ER_E=0\]

\[R_E= \frac{V_{EE}-V_{BE}}{I_E}\]

\[R_E=\frac{5-0.7}{1.5m}=4.5k \Omega\]

KVL at the output loop. 

Keep in mind that common base configuration has unity current gain and hence IC = IE.

\[-V_{CC}+V_{CB}+I_CR_C=0\]

\[R_C= \frac{V_{CC}-V_{CB}}{I_C}\]

\[R_C=\frac{15-7.5}{1.5m}=5k \Omega\]

Example # 4: Calculate RC & RE. 

\[I_E=2mA\]

\[V_{CB} =9V\]

KVL at the input loop. 

\[-V_{EE}+V_{BE}+I_ER_E=0\]

\[R_E= \frac{V_{EE}-V_{BE}}{I_E}\]

\[R_E=\frac{10-0.7}{2m}=4.7k \Omega\]

KVL at the output loop.

\[-V_{CC}+V_{CB}+I_CR_C=0\]

\[R_C= \frac{V_{CC}-V_{CB}}{I_C}\]

\[R_C=\frac{20-9}{2m}=5.5k \Omega\]

Example # 5: Calculate RB and RC.

Bias point values.

\[V_{CE}=6V\]

\[I_C=2mA\]

\[I_B=\frac{I_C}{\beta}=20\mu A\]

Find the possible bias point values for  β = 50 - 150.

KVL at the input loop, and evaluate RB.

\[-V_{CC}+I_BR_B+0V_{BE}=0\]

\[R_B= \frac{V_{CC}-V_{BE}}{I_B}\]

\[R_B=\frac{12-0.7}{2 \mu}=565k \Omega \text {  equation 1  }\]

KVL at the output loop, and evaluate RC.

\[-V_{CC}+I_CR_C+V_{CE}=0\text {  equation 2  }\]

\[R_C= \frac{V_{CC}-V_{CE}}{I_C}\]

\[R_C=\frac{12-6}{2m}=3k \Omega\]

For β = 50 and  β = 150: Calculate minimum and maximum IC and VCE.

From equation 1:

\[I_B=\frac{12-0.7}{565k}=20 \mu A\]

\[I_{C(min)}=\beta_{min}I_B\]

\[I_{C(min)}=50*20 \mu = 1mA\]

\[I_{C(max)}=\beta_{max}I_B\]

\[I_{C(max)}=150*20 \mu = 3mA\]

From equation 2:

\[V_{CE(min)}=V_{CC}-I_{C(max)}R_C\]

\[V_{CE(min)}=12-3m*3k=3V\]

\[V_{CE(max)}=V_{CC}-I_{C(min)}R_C\]

\[V_{CE(max)}=12-1m*3k=9V\]

IC may vary from 1mA to 3mA.

VCE may vary from 3V to 9V.

Example # 6: Find RB and RC.

\[V_{CE}=5V\]

\[I_C=1mA\]

\[V_{CC}=15V\]

\[\beta = 100\]

\[I_B=10 \mu A\]

Find the possible bias point values for  β = 30 - 150.

KVL at the input loop, and evaluate RB.

\[-V_{CC}+I_BR_B+0V_{BE}=0\]

\[R_B= \frac{V_{BB}-V_{BE}}{I_B}\]

\[R_B=\frac{15-0.7}{ 10 \mu}=1.4M \Omega \text {  equation 1  }\]

KVL at the output loop, and evaluate RC.

\[-V_{CC}+I_CR_C+V_{CE}=0\text {  equation 2  }\]

\[R_C= \frac{V_{CC}-V_{CE}}{I_C}\]

\[R_C=\frac{15-5}{1m}=10k \Omega\]

For β = 30 and  β = 150: Calculate minimum and maximum IC and VCE.

From equation 1:

\[I_B=\frac{15-0.7}{1.4M}=10 \mu A\]

\[I_{C(min)}=\beta_{min}I_B\]

\[I_{C(min)}=30*10 \mu = 0.3mA\]

\[I_{C(max)}=\beta_{max}I_B\]

\[I_{C(max)}=150*10 \mu = 1.5mA\]

From equation 2:

\[V_{CE(min)}=V_{CC}-I_{C(max)}R_C\]

\[V_{CE(min)}=15-1.5m*10k=0V\]

\[V_{CE(max)}=V_{CC}-I_{C(min)}R_C\]

\[V_{CE(max)}=15-0.3m*10k=12V\]

IC may vary from 0.3 mA to 1.5 mA.

VCE may vary from 0V to 12V.

Example # 7:

Bias point values VCE and IE are given.

\[V_{CE}=16V\]

\[I_E=4mA\]

\[V_{CC}=24V\]

\[\beta = 100\]

\[I_B=\frac{I_E}{\beta} =0.4 \mu A\]

Apply KVL at the output loop, and evaluate RE.

\[-V_{CC}+V_{CE}+I_ER_E=0\]

\[R_E=\frac{V_{CC}-V_{CE}}{I_E}\]

\[R_E=\frac{24-16}{4m}=2k \Omega\]

Apply KVL at the input loop, and evaluate RB.

\[-V_B+I_BR_B+V_{BE}+I_ER_E=0\]

\[R_B=\frac{V_B-V_{BE}-I_ER_E}{I_B}\]

\[R_B=\frac{24-0.7-4m*2k}{0.4 \mu}=382.5k \Omega\] 

Example # 8:

Bias point values VCE and IE are given.

\[V_{CE}=12V\]

\[I_E=10mA\]

\[V_{CC}=30V\]

\[\beta = 100\]

\[I_B=\frac{I_E}{\beta} = 100 \mu A\]

Apply KVL at the output loop, and evaluate RE.

\[-V_{CC}+V_{CE}+I_ER_E=0\]

\[R_E=\frac{V_{CC}-V_{CE}}{I_E}\]

\[R_E=\frac{30-12}{10m}=1.8k \Omega\]

Apply KVL at the input loop, and evaluate RB.

\[-V_B+I_BR_B+V_{BE}+I_ER_E=0\]

\[R_B=\frac{V_B-V_{BE}-I_ER_E}{I_B}\]

\[R_B=\frac{30-0.7-10m*1.8k}{100\mu}=113k \Omega\] 

Example # 9:

\[V_C=5V\]

\[I_C=I_E=2mA\]

Apply KVL at the input loop, and evaluate RE.

\[V_{BE}+I_ER_E-V_{EE}=0\]

\[R_E=\frac{V_{EE}-V_{BE}}{I_E}\]

\[R_E=\frac{15-0.7}{2m}=7k \Omega\]

To determine RC, find voltage across RC:

\[I_CR_C=V_{CC}-V_C\]

\[R_C=\frac{V_{CC}-V_C}{I_C}=\frac{15-5}{2m}=5k \Omega\]

Example # 10: Find Out the highest possible voltage at the base for which the transistor is in active mode.

Maximum base voltage means the base voltage at which collector current is maximum. But it should remain in active mode.

Saturation occurs at VCE > 0.2V. Let's calculate maximum collector current just before the saturation mode. At this point, VCE = 0.3V.

Apply KVL at the output loop and figure out the collector current IC.

\[-V_{CC}+I_CR_C+V_{CE}+I_ER_E=0\]

\[I_C=I_E\]

\[-10+I_C(R_C+R_E)+V_{CE}=0\]

\[I_C=\frac{10-0.3}{8k}=1.2 mA\]

Apply KVL at the output loop and figure out the base voltage VB.

\[-V_B+V_{BE}+I_ER_E=0\]

\[V_B=4.7V\]

Example # 11: Find Out RE and RC.

\[V_C=5V\]

\[I_C=I_E=0.5mA\]

\[V_{CB}=2V\]

Reverse biased voltage at base collector junction.

Apply KVL at the output loop and figure out the base voltage RE.

\[-V_B+V_{BE}+I_ER_E=0\]

\[R_E=6.6k \Omega\]

As you know,

\[V_{CB}=V_C-V_B\]

\[V_C=4+2=6V\]

For RC, 

\[R_C=\frac{V_{CC}-V_C}{I_C}\]

\[R_C=\frac{10-6}{0.5m}=8k \Omega\]

Example # 12: Find the value of RC to which the transistor remains in active mode.

A PNP transistor is given. Apply KVL at the input loop, and evaluate IE.

\[-10+I_ER_E+V_{EB}=0\]

\[I_E=\frac{10-0.7}{2k}=4.6mA\]

VEC<0.3V, this condition is for saturation mode. The transistor remains in active mode, to fulfill this requirement, suppose VEC=0.3V.

Apply KVL at the output loop and evaluate RC.

\[-10+I_CR_C+V_CE+I_ER_E=0\]

\[I_C=I_E\]

\[R_C=4.65k \Omega\]

Example # 13: Determine RC and RE

\[I_C=I_E=1mA\]

A PNP transistor is given. Apply KVL at the input loop, and evaluate RE.

\[-10+I_ER_E+V_{EB}=0\]

\[R_E=\frac{10-0.7}{1m}=9.3k \Omega\]

In this example, VC (that is collector voltage is given. 

\[V_C=V_{CC}+I_CR_C\]

\[-4=-10+1m*R_C\]

\[\text { Solve for  }R_C\]

\[R_C=6k \Omega\]