BJT Load Line & Q point Analysis: Complete tutorial with solved examples
- How to select Q point according to the application?
- Centred Q point
- Q point near saturation
- Q point near the cutoff
- How to determine the amplitude of output voltage
This topic helps you to design an amplifier.
Biasing & Selection Of Q Point:
As I discussed, proper biasing is required for different modes of operation. There are three different positions of Q point on a load line. Biasing helps to set the Q point according to your needs.
Centered Q Point:
Maximum possible peak to peak voltage or maximum AC output compliance can achieve with the help of a centred Q point.
When the Q point is in the middle of the load line, then
ICQ*rC = VCEQ equation 3
And hence output signal swings equally above and below the Q point without any clipping or distortion. It means the transistor drives into an active region.
Example 1:
 |
| Fig 1 Schematic for centred Q point |
Step 1: Find DC load line
KVL at the output circuit
-VCC + ICRC + VCE = 0
-10 + 1k*IC + VCE = 0 … eq 1.1
Substitute VCE = 0 in eq 1.1 for a point on the y-axis
IC = 10mA
Substitute IC = 0 in eq 1.1 for a point on the x-axis
VCE = 10V
Step 2: Find Q point
KVL at the input circuit
-VCC + IBRB + VBE = 0
IC = β*IB
-10 + ICQ*140k/100 + 0.7 = 0
ICQ = 6.6mA
KVL at the output circuit
-VCC + ICRC + VCEQ = 0
-10 + 6.6m*1k + VCEQ = 0
VCEQ = 3.4V
Step 3: Find AC load line
iC(sat) = ICQ + VCEQ/rC
rC = RC||RL
iC(sat) = 6.6m + 3.4/500
iC(sat) = 6.6m + 6.8m
iC(sat) = 13.4mA
vce(cut) = VCEQ + ICQ*rC
vce(cut) = 3.4 + 6.6m*500
vce(cut) = 6.7V
Step 4: Evaluate Output Compliance:
ICQ*rC = VCEQ
6.6m*500 = 3.4
3.3 ~ 3.4
Results:
| Fig 2 Q point at the centre of AC load line |
Look at the graph shown in the figure, you can easily understand by visualizing the graph. You can see VCEQ is almost equal to ICQ*rC. And hence signal swings equally on both sides of the Q point.
Q Point Near Saturation:
When the Q point is above the midpoint of an AC load line then equation 3 becomes
ICQ*rC > VCEQ
In this case, the output swing is limited by VCEQ. This type of clipping means the transistor drives into the saturation region.
Example 2:
 |
| Fig, 3 Schematic for Q point near saturation |
Step 1: Find DC load line
KVL at the output circuit
-VCC + ICRC + VCE = 0
-10 + 1k*IC + VCE = 0 … eq 2.1
Substitute VCE = 0 in eq 2.1 for a point on the y-axis
IC = 10mA
Substitute IC = 0 in eq 2.1 for a point on the x-axis
VCE = 10V
Step 2: Find Q point
KVL at the input circuit
-VCC + IBRB + VBE = 0
IC = β*IB
-10 + IC*120k/100 + 0.7 = 0
ICQ = 7.75mA
KVL at the output circuit
-VCC + ICRC + VCE = 0
VCEQ = 10 - 7.75
VCEQ = 2.25V
Step 3: Find AC load line
iC(sat) = ICQ + VCEQ/rC
rC = RC||RL
iC(sat) = 7.75m + 2.25/500
iC(sat) = 12.25mA
vce(cut) = VCEQ + ICQ*rC
vce(cut) = 2.25 + 7.75m*500
vce(cut) = 6.125V
Step 4: Evaluate Output Compliance:
Check for both compliances.
PP =2* VCEQ = 4.4V
PP = 2*ICQ*rC = 7.7
Amplifier compliance is the smaller value, which is 4.4V.
Results:
| Fig 4 Q point lies near saturation region or above the middle point of AC load line |
Look at the graph shown in the figure, you can easily understand by visualizing the graph. The signal clips near the saturation region. Also, ICQ*rC is greater than VCEQ.
Q Point Near Cut off:
When the Q point is below the midpoint of an AC load line then equation 3 becomes
ICQ*rC < VCEQ
In this case, the output swing is limited by ICQ*rC. This type of clipping means the transistor drives into the cut off region.
Example 3:
 |
| Fig 5 Schematic for Q point near cut off |
Step 1: Find DC load line
KVL at the output circuit
-VCC + ICRC + VCE = 0
-10 + 1k*IC + VCE = 0 … eq 3.1
Substitute VCE = 0 in eq 3.1 for a point on the y-axis
IC = 10mA
Substitute IC = 0 in eq 3.1 for a point on the x-axis
VCE = 10V
Step 2: Find Q point
KVL at the input circuit
-VCC + IBRB + VBE = 0
IC = β*IB
-10 + ICQ*180k/β + 0.7 = 0
ICQ = 5.2mA
KVL at the output circuit
-VCC + ICRC + VCE = 0
-10 + 5.2m*1k + VCEQ = 0
VCEQ = 4.8V
Step 3: Find AC load line
iC(sat) = ICQ + VCEQ/rC
rC = RC||RL
iC(sat) = 5.2m + 4.8/500
iC(sat) = 14.8mA
vce(cut) = VCEQ + ICQ*rC
vce(cut) = 4.8 + 5.2m*500
vce(cut) = 7.4V
Step 4: Evaluate Output Compliance:
Check for both compliances.
PP =2* VCEQ = 9.6V
PP = 2*ICQ*rC = 5.2V
Amplifier compliance is the smaller value, which is 5.2V.
Results:
| Fig 6 Q point near cut off or lies below the midpoint of AC load line |
Look at the graph shown in the figure, you can easily understand by visualizing the graph. I have marked VCEQ and ICQ*rC. You can see VCEQ is greater than ICQ*rC. And hence the signal clips near the cut-off region.
Conclusion:
- Have you noted, the DC load line remains the same in all three examples. Because it has a slope of 1/RC. RC remains the same in all examples
- AC Load Line varies with change in RB
- As RB increases, IB decreases (and hence IC decreases)
- Higher values of RB drives the BJT in cut off mode
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