Showing posts with label BJT. Show all posts
Showing posts with label BJT. Show all posts

DC Analysis BJT (Numericals, Design Problems) part 3

DC Analysis BJT (, Numericals, Design Problems) part 3

 This is another tutorial on BJT DC analysis. This tutorial is important from a design perspective. How to set circuit parameters, to work in an active mode, or in saturation mode or cut-off mode. For example, change in base and collector resistors (RC and RB) will result in changes in the base and collector currents. This change will have a direct impact on the operating mode of the transistor. The design problems are a little bit tricky. So, let's get started.

Example # 1: Calculate RB, RC and RE.





\[I_{CQ}=\frac{1}{2}I_{C(sat)}\]

\[I_{C(sat)}=8mA=4mA\]

\[V_C=18V\]

\[\beta=110\]


Apply KVL at the input loop.

\[-V_B+I_BR_B+V_{BE}+I_ER_E=0 \text {  equation 1}\]


\[I_C=\beta I_B\]

\[I_B=36\mu A\]


\[I_E =I_C+I_B\]

\[I_E=4.036mA\]


Calculate RC.

\[ R_C=\frac{V_{CC}-V_C}{I_{CQ}}\]

\[R_C=2.5k\Omega\]


 and RE set the Q point value and slope of the load line.


\[I_{C(sat)} = \frac{V_{CC}}{R_C+R_E}\]

\[R_C+R_E = \frac{28}{8m}=3.5k\Omega\]

\[ R_C = 3.5k-2.5k = 1k \Omega\]


Substitute RE in equation 1 and evaluate RB.


\[-28+36\mu R_B+0.7+4.036m*1k=0\]

\[R_B=646k\Omega\]

Example # 2: Calculate VCC, RC, RB

From load line,

\[V_{CC} = 20V\]

\[I_{C(sat)}=8mA\]

\[I_{BQ}=40 \mu A\]


\[I_{C(sat)}=\frac{V_{CC}}{R_C}\]

\[R_C=2.5k \Omega\]


For RB, apply KVL at the input loop.


\[-V_{CC}+I_B R_B+V_{BE}=0\]

\[-20+40 \mu R_B+0.7=0\]

\[R_B=482k \Omega \]


Example # 3: Design a common base NPN transistor with following parameters.


\[I_E=1.5mA\]

\[V_{CB} =7.5V\]

\[V_{CC}=15V\]

\[V_{CE}=-5V\]


Apply KVL at the input loop.

\[-V_{EE}+V_{BE}+I_ER_E=0\]

\[R_E= \frac{V_{EE}-V_{BE}}{I_E}\]

\[R_E=\frac{5-0.7}{1.5m}=4.5k \Omega\]


KVL at the output loop. 

Keep in mind that common base configuration has unity current gain and hence IC = IE.


\[-V_{CC}+V_{CB}+I_CR_C=0\]

\[R_C= \frac{V_{CC}-V_{CB}}{I_C}\]

\[R_C=\frac{15-7.5}{1.5m}=5k \Omega\]


Example # 4: Calculate RC & RE

\[I_E=2mA\]

\[V_{CB} =9V\]


KVL at the input loop. 

\[-V_{EE}+V_{BE}+I_ER_E=0\]

\[R_E= \frac{V_{EE}-V_{BE}}{I_E}\]

\[R_E=\frac{10-0.7}{2m}=4.7k \Omega\]


KVL at the output loop.

\[-V_{CC}+V_{CB}+I_CR_C=0\]

\[R_C= \frac{V_{CC}-V_{CB}}{I_C}\]

\[R_C=\frac{20-9}{2m}=5.5k \Omega\]



Example # 5: Calculate RB and RC.


Bias point values.

\[V_{CE}=6V\]

\[I_C=2mA\]

\[I_B=\frac{I_C}{\beta}=20\mu A\]

Find the possible bias point values for  β = 50 - 150.


KVL at the input loop, and evaluate RB.

\[-V_{CC}+I_BR_B+0V_{BE}=0\]

\[R_B= \frac{V_{CC}-V_{BE}}{I_B}\]

\[R_B=\frac{12-0.7}{2 \mu}=565k \Omega \text {  equation 1  }\]


KVL at the output loop, and evaluate RC.

\[-V_{CC}+I_CR_C+V_{CE}=0\text {  equation 2  }\]

\[R_C= \frac{V_{CC}-V_{CE}}{I_C}\]

\[R_C=\frac{12-6}{2m}=3k \Omega\]


For β = 50 and  β = 150: Calculate minimum and maximum IC and VCE.


From equation 1:

\[I_B=\frac{12-0.7}{565k}=20 \mu A\]

\[I_{C(min)}=\beta_{min}I_B\]

\[I_{C(min)}=50*20 \mu = 1mA\]


\[I_{C(max)}=\beta_{max}I_B\]

\[I_{C(max)}=150*20 \mu = 3mA\]



From equation 2:

\[V_{CE(min)}=V_{CC}-I_{C(max)}R_C\]

\[V_{CE(min)}=12-3m*3k=3V\]


\[V_{CE(max)}=V_{CC}-I_{C(min)}R_C\]

\[V_{CE(max)}=12-1m*3k=9V\]


IC may vary from 1mA to 3mA.

VCE may vary from 3V to 9V.

Example # 6: Find RB and RC.

\[V_{CE}=5V\]

\[I_C=1mA\]

\[V_{CC}=15V\]

\[\beta = 100\]

\[I_B=10 \mu A\]


Find the possible bias point values for  β = 30 - 150.


KVL at the input loop, and evaluate RB.

\[-V_{CC}+I_BR_B+0V_{BE}=0\]

\[R_B= \frac{V_{BB}-V_{BE}}{I_B}\]

\[R_B=\frac{15-0.7}{ 10 \mu}=1.4M \Omega \text {  equation 1  }\]


KVL at the output loop, and evaluate RC.

\[-V_{CC}+I_CR_C+V_{CE}=0\text {  equation 2  }\]

\[R_C= \frac{V_{CC}-V_{CE}}{I_C}\]

\[R_C=\frac{15-5}{1m}=10k \Omega\]


For β = 30 and  β = 150: Calculate minimum and maximum IC and VCE.


From equation 1:

\[I_B=\frac{15-0.7}{1.4M}=10 \mu A\]

\[I_{C(min)}=\beta_{min}I_B\]

\[I_{C(min)}=30*10 \mu = 0.3mA\]


\[I_{C(max)}=\beta_{max}I_B\]

\[I_{C(max)}=150*10 \mu = 1.5mA\]


From equation 2:

\[V_{CE(min)}=V_{CC}-I_{C(max)}R_C\]

\[V_{CE(min)}=15-1.5m*10k=0V\]


\[V_{CE(max)}=V_{CC}-I_{C(min)}R_C\]

\[V_{CE(max)}=15-0.3m*10k=12V\]


IC may vary from 0.3 mA to 1.5 mA.

VCE may vary from 0V to 12V.

Example # 7:

Bias point values VCE and IE are given.

\[V_{CE}=16V\]

\[I_E=4mA\]

\[V_{CC}=24V\]

\[\beta = 100\]

\[I_B=\frac{I_E}{\beta} =0.4 \mu A\]


Apply KVL at the output loop, and evaluate RE.


\[-V_{CC}+V_{CE}+I_ER_E=0\]

\[R_E=\frac{V_{CC}-V_{CE}}{I_E}\]

\[R_E=\frac{24-16}{4m}=2k \Omega\]


Apply KVL at the input loop, and evaluate RB.

\[-V_B+I_BR_B+V_{BE}+I_ER_E=0\]

\[R_B=\frac{V_B-V_{BE}-I_ER_E}{I_B}\]

\[R_B=\frac{24-0.7-4m*2k}{0.4 \mu}=382.5k \Omega\] 


Example # 8:

Bias point values VCE and IE are given.

\[V_{CE}=12V\]

\[I_E=10mA\]

\[V_{CC}=30V\]

\[\beta = 100\]

\[I_B=\frac{I_E}{\beta} = 100 \mu A\]


Apply KVL at the output loop, and evaluate RE.

\[-V_{CC}+V_{CE}+I_ER_E=0\]

\[R_E=\frac{V_{CC}-V_{CE}}{I_E}\]

\[R_E=\frac{30-12}{10m}=1.8k \Omega\]


Apply KVL at the input loop, and evaluate RB.

\[-V_B+I_BR_B+V_{BE}+I_ER_E=0\]

\[R_B=\frac{V_B-V_{BE}-I_ER_E}{I_B}\]

\[R_B=\frac{30-0.7-10m*1.8k}{100\mu}=113k \Omega\] 


Example # 9:

\[V_C=5V\]

\[I_C=I_E=2mA\]


Apply KVL at the input loop, and evaluate RE.

\[V_{BE}+I_ER_E-V_{EE}=0\]

\[R_E=\frac{V_{EE}-V_{BE}}{I_E}\]

\[R_E=\frac{15-0.7}{2m}=7k \Omega\]


To determine RC, find voltage across RC:

\[I_CR_C=V_{CC}-V_C\]

\[R_C=\frac{V_{CC}-V_C}{I_C}=\frac{15-5}{2m}=5k \Omega\]

Example # 10: Find Out the highest possible voltage at the base for which the transistor is in active mode.


Maximum base voltage means the base voltage at which collector current is maximum. But it should remain in active mode.


Saturation occurs at VCE > 0.2V. Let's calculate maximum collector current just before the saturation mode. At this point, VCE = 0.3V.


Apply KVL at the output loop and figure out the collector current IC.

\[-V_{CC}+I_CR_C+V_{CE}+I_ER_E=0\]

\[I_C=I_E\]

\[-10+I_C(R_C+R_E)+V_{CE}=0\]

\[I_C=\frac{10-0.3}{8k}=1.2 mA\]


Apply KVL at the output loop and figure out the base voltage VB.


\[-V_B+V_{BE}+I_ER_E=0\]

\[V_B=4.7V\]



Example # 11: Find Out RE and RC.

\[V_C=5V\]

\[I_C=I_E=0.5mA\]

\[V_{CB}=2V\]

Reverse biased voltage at base collector junction.


Apply KVL at the output loop and figure out the base voltage RE.


\[-V_B+V_{BE}+I_ER_E=0\]

\[R_E=6.6k \Omega\]


As you know,

\[V_{CB}=V_C-V_B\]

\[V_C=4+2=6V\]


For RC

\[R_C=\frac{V_{CC}-V_C}{I_C}\]

\[R_C=\frac{10-6}{0.5m}=8k \Omega\]

Example # 12: Find the value of RC to which the transistor remains in active mode.

A PNP transistor is given. Apply KVL at the input loop, and evaluate IE.


\[-10+I_ER_E+V_{EB}=0\]

\[I_E=\frac{10-0.7}{2k}=4.6mA\]


VEC<0.3V, this condition is for saturation mode. The transistor remains in active mode, to fulfill this requirement, suppose VEC=0.3V.


Apply KVL at the output loop and evaluate RC.

\[-10+I_CR_C+V_CE+I_ER_E=0\]

\[I_C=I_E\]

\[R_C=4.65k \Omega\]


Example # 13: Determine RC and RE

\[I_C=I_E=1mA\]


A PNP transistor is given. Apply KVL at the input loop, and evaluate RE.


\[-10+I_ER_E+V_{EB}=0\]


\[R_E=\frac{10-0.7}{1m}=9.3k \Omega\]


In this example, VC (that is collector voltage is given. 


\[V_C=V_{CC}+I_CR_C\]

\[-4=-10+1m*R_C\]

\[\text { Solve for  }R_C\]

\[R_C=6k \Omega\]




How To Determine BJT Modes | Operating Region

Identifying The Mode Of The BJT | DC Analysis

 Identifying The Mode Of The BJT (DC Analysis Part 2)


In a continuation of BJT analysis, it is important to have a look at this topic. Most of the time, it is necessary to evaluate the mode of the transistors.


Learning Objectives:

  • How to find the operating region or mode of the BJT?


To find the operating region, we need to find;

  • Junction voltages

  • All currents


Now, it's time to discuss some important variations in parameters in each mode.


Saturation Mode:

In this mode, both junctions are forward biased. You need to calculate these parameters;

  • VBE

  • VCE

  • IC(sat)


First of all you need to check out VBE. If VBE > 0.7 V, the transistor is either in active or saturation mode. Always assume the active mode and proceed with your calculations. Now calculate VCE, if you get absurd results, it means the transistor is in the saturation region.


\[V_{CE(sat)} = 0.2 V\]

\[I_{C(sat)} = \frac{V_{CC}-V_{CE(sat)}}{R_C}\]


Since VCE is very small as compared to VCC, neglect it.

\[I_{C(sat)} = \frac{V_{CC}}{R_C}\]


The base current is significantly high in saturation mode. The minimum value of base current to produce saturation is given below;

\[I_{B(min)} = I_{C(sat)}{\beta_{DC}\]

It is the minimum value of IB to drive the transistor in saturation. IB should be greater than IB(min). It is possible only when βDC is small. β is a device parameter, and it can not be changed. But keep in mind that β is forward current gain and it is for active mode only. βDC has a lower value in saturation mode.

Active Mode:

In this mode, the base emitter junction is forward biased and the base collector junction is reverse biased. 

First of all you need to check out VBE. If VBE > 0.7 V, the transistor is either in active or saturation mode. Always assume the active mode and proceed with your calculations. 


Cut-Off Mode:

It is the easiest mode to analyse. Both junctions are reverse biased. All currents are zero except small leakage current.

\[V_{CE(cut-off)} = V_{CC}\]


You need to evaluate VBE only. If VBE < 0.7 V, the transistor is in cut-off.




Steps to follow:

  • Calculate IC(sat) and VCE(cut) . With the help of these two points you can draw the load line.

  • Assume that the transistor is in active mode.

  • In the next step, apply KVL at the input loop. You will get the IB and hence IC

  • Now apply the KVL equation at the output loop. You will get VCE

  • You get the load line and the Q point (VCE , IC). Plot these two points on the load line. 

  • Compare;

    • VCE > VCE(sat)

    • IC < IC(sat) 

The transistor is in active mode

  • If you get absurd results after calculations, then your assumption is wrong. The transistor is in saturation mode.

Example #1: Determine IC(sat) and VCE(cut-off).



For IC(sat), assume a short between collector and emitter. Because in saturation mode VCE is approximately equal to zero. Apply KVL at the output loop.


\[-V_{CC} + I_CR_C + V_{CE}= 0\]

\[I_{C(sat)} = \frac{20}{3.3k} = 6mA\]


\[V_{CE(cut)} = V_{CC}\]


Example #2:


Now change parameters in figure 1, and determine its mode.


RB = 33kΩ

hfe = β = 100


Assume the transistor is in active mode.


Step 1: Apply KVL at the input loop.


\[-V_{BB}+I_B*R_B+V_{BE}=0\]

\[I_B=\frac {V_{BB}-V_{BE}}{R_B}\]

\[I_B=\frac{10-0.7}{33k}\]

\[I_B=0.28mA\]


\[I_C=\beta I_B\]

\[I_C=100*0.28m = 28mA\]


Step 2: Apply KVL at the output loop.

\[-V_{CC}+I_C*R_C+V_{CE}=0\]

\[-20+28m*3.3k+V_{CE}]=0\]

\[V_{CE}=-72.4V\]


Have a look at VCE. Is it possible to get such results? How do VCE = -72.4V, when the applied voltage is 20V. Similarly, the value of IC = 28mA which is not possible. The assumption goes wrong. The transistor is not in the active mode. Again calculate β , IC(sat) and VCE(sat) for saturation mode.


Calculate β for saturation mode.


\[\beta = \frac {I_C}{I_B}\]

\[\beta = 21.4\]


Calculate IC for saturation which is already calculated.


\[-V_{CC} + I_CR_C + V_{CE}= 0\]

\[I_{C(sat)} = \frac{20}{3.3k} = 6mA\]



Calculate VCE

\[-V_{CC} + I_CR_C + V_{CE}= 0\]

\[-20+6m*3.3k + V_{CE}=0\]

\[V_{CE}=0.2\]


On a final note, look at the value of IB which is quite large, and tends to decrease the value of β. The decreased value of β shows that the transistor is saturated. Aslo, VCE = VCE(sat) = 0.2V. You can check out with the help of a multimeter as well. I attached the schematic and it shows the value of VCE which is quite low and indicates that the transistor is saturated.


Example #3:


Now change parameters in figure 1, and determine its mode.

VBB = 5V

hfe = β = 200

IC(sat) = 6mA (calculated previously)


From the given data, it is evident that the value of voltage at the base (that is VBB) changes will result in change of base current (that is IB). Similarly hfe (that is β) increases will change the base current. Assume the active mode and proceed with calculations.


Step 1: Apply KVL at the input loop.


\[-V_{BB}+I_B*R_B+V_{BE}=0\]

\[I_B=\frac {V_{BB}-V_{BE}}{R_B}\]

\[I_B=\frac{5-0.7}{1M}\]

\[I_B=4.3 \mu A\]


\[I_C=\beta I_B\]

\[I_C=200*4.3 \mu = 0.86mA\]


Step 2: Apply KVL at the output loop.


\[-V_{CC} + I_CR_C + V_{CE}= 0\]

\[-20+0.86m*3.3k + V_{CE}=0\]

\[V_{CE}=17.2V\]


VCE > VCE(sat)

IC < IC(sat) 

The transistor is in active mode.


Example #4:

Now change parameters in figure 1, and determine its mode.

RC = 10kΩ

hfe = β = 50


The value of RC changes, will result in a changed value of IC(sat). Assume the transistor is in active mode and proceed with calculations.


Calculate IC(sat) first. Assume VCE = 0.


\[-V_{CC} + I_CR_C + V_{CE}= 0\]

\[I_{C(sat)} = \frac{20}{10k} = 2mA\]


\[V_{CE(cut)} = V_{CC}\]


Step 1: Apply KVL at the input loop.


\[-V_{BB}+I_B*R_B+V_{BE}=0\]

\[I_B=\frac {V_{BB}-V_{BE}}{R_B}\]

\[I_B=\frac{10-0.7}{1M}\]

\[I_B=9.3 \mu A\]


\[I_C=\beta I_B\]

\[I_C=50*9.3 \mu = 0.46mA\]


Step 2: Apply KVL at the output loop.

\[-V_{CC} + I_CR_C + V_{CE}= 0\]

\[-20+0.46m*10k + V_{CE}=0\]

\[V_{CE}=15.4V\]


VCE > VCE(sat)

IC < IC(sat) 

The transistor is in active mode.


Example #5:

Now change parameters in figure 1, and determine its mode.

VCC = 10V

hfe = 100


Calculate IC(sat). for this calculation, set VCE(sat) = 0.


\[-V_{CC} + I_CR_C + V_{CE}= 0\]


\[I_{C(sat)} = \frac{V_{CC}}{R_C}\]

\[I_{C(sat)} = \frac{10}{3.3k}\]

\[I_{C(sat)} = 3mA\]


\[V_{CE(cut)} = V_{CC}\]


Assume that the transistor is in active mode.


Step 1: Apply KVL at the input loop.

\[-V_{BB}+I_B*R_B+V_{BE}=0\]

\[I_B=\frac {V_{BB}-V_{BE}}{R_B}\]

\[I_B=\frac{10-0.7}{1M}\]

\[I_B=9.3 \mu A\]


\[I_C=\beta I_B\]

\[I_C=100*9.3 \mu = 0.93mA\]


Step 2: Apply KVL at the output loop.

\[-V_{CC} + I_CR_C + V_{CE}= 0\]

\[-10+0.93m*3.3k + V_{CE}=0\]

\[V_{CE} = 6.9V\]


VCE > VCE(sat)

IC < IC(sat) 

The transistor is in active mode.

Example #6:

Various sets of parameters are given for the circuit. Determine the mode of the transistor accordingly. 


Calculate IC(sat) and VCE(cut). This is for the load line.


\[I_{C(sat)}=\frac {V_{CC}}{R_C}\]

\[I_{C(sat)}=\frac{5}{479}=11mA\]



\[V_{CE(cut)} = V_{CC}\]


Assume that the transistor is in active mode.


Step 1: Apply KVL at the input loop.


\[-V_{BB}+I_B*R_B+V_{BE}=0\]

\[I_B=\frac {V_{BB}-V_{BE}}{R_B}\]

\[I_B=\frac{5-0.7}{680k}\]

\[I_B=6.3 \mu A\]


\[I_C=\beta I_B\]

\[I_C=100*9.3 \mu = 0.63mA\]


Step 2: Apply KVL at the output loop.

\[-V_{CC} + I_CR_C + V_{CE}= 0\]

\[-5+0.63m*470 + V_{CE}=0\]

\[V_{CE} = 4.7V\]


VCE > VCE(sat)

IC < IC(sat) 

The transistor is in active mode.

Example #7:

Now change parameters in figure 6, and determine its mode.

RB = 47kΩ

hfe = β = 100


Step 1: Apply KVL at the input loop.


\[-V_{BB}+I_B*R_B+V_{BE}=0\]

\[I_B=\frac {V_{BB}-V_{BE}}{R_B}\]

\[I_B=\frac{5-0.7}{47k}\]

\[I_B=91 \mu A\]


\[I_C=\beta I_B\]

\[I_C=100*91 \mu = 9.1 mA\]


Step 2: Apply KVL at the output loop.

\[-V_{CC} + I_CR_C + V_{CE}= 0\]

\[-5+9.1m*470 + V_{CE}=0\]

\[V_{CE} = 0.72V\]


VCE > VCE(sat)

IC < IC(sat) 

The transistor is in active mode.


Example #8:

Now change parameters in figure 6, and determine its mode.

VBB = 10V

hfe = β = 500


Step 1: Apply KVL at the input loop.


\[-V_{BB}+I_B*R_B+V_{BE}=0\]

\[I_B=\frac {V_{BB}-V_{BE}}{R_B}\]

\[I_B=\frac{10-0.7}{680k}\]

\[I_B=13.6 \mu A\]


\[I_C=\beta I_B\]

\[I_C=500*13.6 \mu = 6.8 mA\]


Step 2: Apply KVL at the output loop.

\[-V_{CC} + I_CR_C + V_{CE}= 0\]

\[-5+6.8m*470 + V_{CE}=0\]

\[V_{CE} = 1.78V\]


VCE > VCE(sat)

IC < IC(sat) 

The transistor is in active mode.


Example #9:


Now change parameters in figure 6, and determine its mode.

RC = 10kΩ

hfe = β = 100


Calculate IC(sat)

\[-V_{CC} + I_CR_C + V_{CE}= 0\]

\[-5+I_C*10k + V_{CE}=0\]

VCE = 0.2 for saturation

\[I_{C(sat)} = \frac{5-0.2}{10k}\]

\[I_{C(sat)} = 0.48mA\]



Step 1: Apply KVL at the input loop.


\[-V_{BB}+I_B*R_B+V_{BE}=0\]

\[I_B=\frac {V_{BB}-V_{BE}}{R_B}\]

\[I_B=\frac{5-0.7}{680k}\]

\[I_B=6.3 \mu A\]


\[I_C=\beta I_B\]

\[I_C=100*6.3 \mu = 0.6 mA\]


Step 2: Apply KVL at the output loop.

\[-V_{CC} + I_CR_C + V_{CE}= 0\]

\[-5+0.6m*10k + V_{CE}=0\]

\[V_{CE} = -1.3 V\]


VCE < VCE(sat)

IC > IC(sat) 



The assumption goes wrong. The transistor is in saturation mode. The calculated value of IC is greater than IC(sat) . Which is not possible. Discard IC = 6mA. The maximum possible current is IC(sat) = 0.48 mA.  The value of VCE is also an absurd value. We need to recalculate VCE with the help of IC(sat).


\[-V_{CC} + I_CR_C + V_{CE}= 0\]

\[-5+0.48m*10k + V_{CE}=0\]

\[V_{CE} = 0.2 V\]



Example #10:


Now change parameters in figure 6, and determine its mode.

VCC = 10V

hfe = β = 100


VCC changes, it will change the value of IC(sat). Calculate IC(sat)

\[-V_{CC} + I_CR_C + V_{CE}= 0\]

\[-10+I_C*470 + V_{CE}=0\]

VCE = 0.2 for saturation

\[I_{C(sat)} = \frac{10-0.2}{10k}\]

\[I_{C(sat)} = 0.21mA\]


VCE(cut) = VCC


Step 1: Apply KVL at the input loop.


\[-V_{BB}+I_B*R_B+V_{BE}=0\]

\[I_B=\frac {V_{BB}-V_{BE}}{R_B}\]

\[I_B=\frac{5-0.7}{680k}\]

\[I_B=6.3 \mu A\]


\[I_C=\beta I_B\]

\[I_C=100*6.3 \mu = 0.6 mA\]


Step 2: Apply KVL at the output loop.

\[-V_{CC} + I_CR_C + V_{CE}= 0\]

\[-10+0.6m*470 + V_{CE}=0\]

\[V_{CE} = 9.7 V\]


VCE > VCE(sat)

IC < IC(sat) 


Active mode is detected.


Lastly:

I have given a tremendous amount of time in creating this article. Time is really precious to me because of a busy schedule.  If you like this tutorial, please drop a comment and like my Facebook page. 

Please check part 1 of this tutorial in the link below.

 BJT DC Analysis Part 1

 





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