Load Line Analysis (BJT) With Solved Examples

Load line and Q point 

Outline:

• Determine biasing, Q point, and DC load line
• Compute Q point

BJT Load Line & Q point Analysis: Complete tutorial with solved examples

AC load line

Variation of Q point and voltage swing limitations

Variation of Q point with different circuit parameters

I talked about the different modes of operation. To operate a transistor in a particular mode of opration, you need proper biasing. In simple terms, biasing means apply potential or voltage to the input and output terminal of the transistor to get the desired mode of operation. 

In BJT analysis, a load line is a line drawn over collector curves to show every possible operating point of a transistor. Or on a load line, there are valid values of IC and VCE.

I am going to consider a base bias amplifier circuit. Although this biasing technique has many flaws it is a simple circuit and a beginner can easily understand this. 

Figure: Base biased amplifier circuit

The purpose of this section is to plot the DC load line:

The DC load line contains possible DC values of IC and VCE for a given amplifier.

To draw a line you need two points (according to mathematics). The load line is drawn between these two extremes is the saturation point and the cut-off point. We need to find out at what point collector current is maximum (that is the saturation point). And the second point is the maximum possible collector to emitter voltage (that is the cut off point).

Method:

You can locate saturation and cut off point with the help of circuit analysis methods that is KVL and KCL.

Look at the circuit in figure 1. The DC equivalent of this circuit is given below. 

Figure: DC equivalent circuit

Look at the simple circuit below. Apply KVL to the output side.

-VCC + ICRC + VCE  = 0

ICRC = VCC - VCE

IC = (VCC - VCE )/RC 

IC = VCC/RC - VCE/RC .. equation 1

Equation 1 is the equation for the load line. We have to draw it over output characteristics curves. 

Look at equation 1, and compare it with the straight-line equation.

y = mx + c

Here, c = VCC/RC 

And  m = slope = -1/RC 

For y-intercept, x = 0 (that is VCE = 0)

IC = VCC/RC … Point 1

For x-intercept, y = 0 (that is IC = 0)

VCE = VCC … Point 2

Figure: load line and Q point general formula

Look at point 1, it is the extreme of saturation region while point 2 is the extreme of the cut off region.

I have plotted the line by joining Point 1 and Point 2 over the characteristic curves. This is the load line. The line intersects the curve at the Q point. It means the Q point is determined by IC and VCE. 

Point 1 intersects the curve at the saturation region of collector curves. It tells you the maximum collector current for the circuit.  While point 2 intersects the curve at the cut off region of collector curves. This point tells you the maximum collector-emitter voltage for the circuit. 

Plotting The Q Point:

You have successfully drawn a load line. Now the second step is to locate a Q point. 

Consider DC equivalent circuit in fig 2,

Apply KVL to the input side

-VCC + IBRB + VBE = 0

IB = (VCC - VBE)/RB

ICQ = βIB

Apply KVL to the output side

-VCC + ICRC + VCE = 0

VCEQ = VCC - ICQRC

Steps involved in load line and Q point analysis:

• Draw DC equivalent circuit
• In DC analysis we assume all the capacitors are open circuit
• Apply KVL to the input side and find out ICQ
• Apply KVL to the output side and find out VCEQ
• Find out maximum collector current IC(sat). You need to consider VCE = 0
• Find out a maximum collector to emitter voltage VCE(cut off). You need to consider IC = 0
• Draw the load line
• Locate the Q point with the help of calculated values of ICQ and VCEQ

Example#1:

Figure: Base biased amplifier

Apply KVL to the input side:

-VCC + IBRB + VBE = 0 

IB = (VCC - VBE)/RB

IB = (10-0.7)/300k

IB = 31 μA

IC = βIB

Consider β = 100

ICQ= 3.1 mA

Apply KVL to the input side:

-VCC + ICRC + VCE = 0… equation 1

VCE = VCC - ICRC

VCE = 10 - 3.1 m*2k

VCEQ = 3.8 V 

Equation 1 is the load line equation

-VCC + ICRC + VCE = 0

For maximum collector current IC(sat), substitute VCE = 0

IC(sat) = VCC/RC

IC(sat) = 10/2k

IC(sat) = 5 mA

For maximum collector to emitter voltage VCE(cut off), substitute IC = 0

  VCE = VCC

VCE(cut off) = 10 V

Figure: Load line and Q point 

Conclusion:

It is all about DC load line analysis. There is an AC load line as well. It is an important topic in designing a BJT based circuit. The two load lines must consider while designing an amplifier circuit. 

Difference Between BJT Configurations

Compare Common Emitter, Common Collector and Common Base Configuration

The article is about all three BJT configurations and their characteristics. You can compare input dynamic resistance Ri, output dynamic resistance RO, current amplification factor Ai, voltage gain AV, power gain AP for different transistor configuration.

Each configuration has its characteristics and area of applications. 

Let's get started. 

Characteristics	Common Emitter	Common Collector	Common Base
Common Terminal	Emitter	Collector	Base
Input Current	IB	IB	IE
Input Voltage	VBE	VBC	VEB
Input Terminal	Base	Base	Emitter
Output Current	IC	IE	IC
Output Voltage	VCE	VEC	VCB
Output Terminal	Collector	Emitter	Collector
Input Dynamic Resistance Ri	High 500 - 5KΩ	Highest 150 - 600KΩ	Low 50 - 500Ω
Output Dynamic Resistance RO	Low 50-500KΩ	Low  100 - 1000Ω	Highest 1 - 10 MΩ
Current Gain Ai	Beta is about 99 β = IC/IB	High (Beta is about 99)	Alpha is less than unity
Voltage Gain Av	High	Less than or equal to unity	High
Power Gain AP	Highest	Less than or equal to unity	Medium
Phase Shift	180° out of phase	0°	0°
Applications	Audio applications	Impedance matching network	High-frequency applications

I have written comprehensive articles on these configurations.

• Common Collector or Emitter Follower Configuration
• Common Base Configuration
• Common Emitter Configuration

Common Base CB Configuration

Common Base Configuration

Look at the figure, the input is applied to the emitter terminal and output is obtained from the collector.  Whereas base is a common terminal to both the input and output signal. The common base configuration has low input impedance and high output impedance. Unity current gain and high voltage gain. 

Biasing Of CB Configuration:

Figure 1 (a) shows the CB configuration and figure 1 (b) shows a biased NPN transistor. Now let me explain how to bias a CB transistor configuration. 

• To analyse input and output characteristics of CB configuration, the transistor should be in active mode
• For active mode, base-emitter junction is forward biased and base-collector junction is reverse biased
• To forward bias base-emitter junction, connect the positive terminal of supply to base and negative terminal to the emitter.
• To reverse bias the collector-base junction, connect the positive terminal of supply to the collector and the negative terminal to the base

Input Characteristics Of CB Configuration:

The graph plotted between input current that is emitter current IE and input voltage (emitter to base voltage) VEB at constant output voltage (collector to base voltage) VCB. IE is plotted along the y-axis and VEB along the x-axis.

The input characteristics of CB configuration is exactly similar to CE input characteristics. In CE, the input characteristics curve is plotted between IB and VBE. Since the base emitter junction is forward biased, we expect a similar graph to a forward-biased diode. 

Understanding the effect of VCB on input characteristics curve:

IE increases with increasing VEB. This is the property of a forward-biased diode. Nothing is new. Now understand the effect of VCB on IE.

As you know reverse bias enhances minority carriers. VCB is a reverse biasing voltage. It reverse biases the collector-base junction. The higher value of VCB increases the width of the depletion region at the base-collector junction. As a result, the effective width of the base decreases. Due to a decrease in effective base width, the concentration gradient of holes in the base increases. In other words, there are more charge particles (holes) per unit area. The increased concentration of holes in the base region causes the diffusion of electrons from the emitter. This increases emitter current IE.

And hence, an increase in VCB will increase in IE. 

Output Characteristics Of CB Configuration:

It is the graph plotted between output current (collector current) IC and output voltage (collector to base voltage) VCB at constant input current IE. IC is plotted along the y-axis and VCB along the x-axis.

By observations, the output characteristics of CB is quite similar to CE and CC configuration. The difference is, the saturation region is on the left side of the y-axis (VCB is negative). 

In figure 1(d) each curve starts at IC = 0. IC increases as an increase in VCB. Forward biasing collector-base junction (VCB) causes IC to increase exponentially.  

Current Amplification Of Common Base Configuration:

The current amplification of common Base configuration is less than unity. As you know the current amplification factor is defined by the ratio of output current to the input current. Here input current is IE and outputs current is IC. Hence the current amplification factor is 

α = IC / IE

Since IC is approximately equal to IE , but always less than IE. Hence α is less than unity. 

Input Resistance Of Common Base Configuration:

It has low input resistance. In this configuration, the input resistance is the ratio of base to collector voltage VBE to the base current IB. At constant output voltage VCB

Ri = VEB / IB

Since IB is very small, VBE is also small (VBE = 0.7V). Ri is much smaller than CE and CC configuration.

Output Resistance Of Common Base Configuration:

In CB configuration, output resistance is the ratio of output voltage VCB to the output current IC. At constant  input current IE.

RO = VCB / IC

Voltage Gain Of CB Configuration:

As I discussed earlier, voltage gain is the ratio of output voltage to the input voltage. The output resistance of BJT in the common base configuration is very high. The load resistor (has a small resistance) is in parallel output resistance of BJT. All current will flow through RL. 

AV = vcb / veb

AV = icRL / ieRi

AV = αieRL / ieRi

AV = αRL / Ri

Power Gain:

Power gain is defined as the ratio of output power to input power. 

Instantaneous input power Pi = i2eRi

Instantaneous output power Po  = i2cRL = α2i2eRL

AP = Po/Pi

AP = α2i2eRL / i2eRi

AP = α2RL / Ri

Other Configurations:

• Common Emitter Configuration
• Common Collector Configuration