The Ebers Moll Model For Bipolar Junction Transistor

Our next goal is to study different BJT models. To study transistor modelling we can not skip this topic. Ebers Moll model (EM model), is an ideal model, giving transistor's working in all modes of operation that are active, reverse active, saturation and cut-off regions. Because of simplicity, it is extensively used in the SPICE model. In this model, the following assumptions are made.

• Base spreading resistance can be neglected

• Diode current is ideal

As you know a transistor has two PN junctions (or PN diodes). This can be viewed as two back to back diodes with a common terminal in between two diodes. These are the emitter-base junction or diode and collector-base junction or diode.

According to this model, the BJT can be replaced by

• Two diodes DE and DC. These two diodes represent base-emitter and base-collector diodes

• Two dependent sources. These current sources depend upon current through diodes.

Figure 1: Ebers Moll Model for NPN transistor

The Ebers Moll model is shown in figure 1.  Ebers and Moll developed a composite model. This model is versatile and still, it is used. This model can predict all four modes of BJT.

Recall some basic concepts about transistors: 

• BJT is not a symmetrical device because the collector has a much larger area than the emitter

• Since collector has a larger area than larger-scale current than emitter scale current ISC>ISE

• The collector current is independent of the collector voltage. This condition holds as long as collector-base junction reverse biased

• A transistor is in the active region if the collector base junction is reverse biased (VCB > 0)

• In the active region, the collector behaves as a constant current source

• This collector current source is current-controlled. When VBE is greater than 0.7V, the device starts. The emitter injects electrons into the thin base

• Because of these emitter electrons, the current of αIE flows in the collector

• In saturation region

Ebers Moll Model & Modes Of Operation:

Now let's understand the EM model. The model consists of two diodes and two controlled current sources.

The diode DC shows collector-base junction, with current IDC and has a scale current ISC. Similarly, the diode DE shows an emitter-base diode, with current IDE and has a scale current ISE.

The diode current IDC and IDE is written as

\[i_{DE} = I_{SE}*(e^{\frac{V_{BE}}{V_{T}}} -1)\Rightarrow equation 1\]

\[i_{DC} = I_{SC}*(e^{\frac{V_{BC}}{V_{T}}} -1)\Rightarrow equation 2\]

As I discussed earlier, this model can predict all possible modes of operation. I am going to prove this statement.

• There is a formula that relates the two-scale currents ISC and ISE

\[α_{F}I_{SE} = α_{R}I_{SC} = I_{S}\]

• First write an equation of currents written on the figure (the EM model). From KCL we get, the terminal currents in terms of αR and αF

\[i_{E} = i_{DE} - α_{R}i_{DC} \Rightarrow 3 \]

\[i_{C} = -i_{DC} + α_{F}i_{DE} \Rightarrow 4 \]

\[i_{B} = (1- α_{F})i_{DE} + (1- α_{R})i_{DC} \Rightarrow 5\]

Evaluation Of Ebers Moll Model Equations

• Substitute diode currents iDE and iDC from equation 1 and equation 2 in equation 3, equation 4 and equation 5

• After substitution, we get terminal current that is iB, iC, iE in terms of terminal voltages vBC and vBE. These equations are called Ebers Moll Model equations for bipolar junction transistors

\[i_{E} = I_{SE}\left(e^{\frac{V_{BE}}{V_{T}}}-1\right) - α_{R}I_{SC}\left(e^{\frac{V_{BC}}{V_T}}-1\right) \Rightarrow A \]

\[i_{C} = - I_{SC}\left(e^{\frac{V_{BC}}{V_T}}-1\right) + α_{F}I_{SE}\left(e^{\frac{V_{BE}}{V_{T}}} -1 \right) \Rightarrow B \]

\[i_B = \left(1- α_{F}\right)I_{SE}\left(e^{\frac{V_{BE}}{V_T}}-1\right) + \left(1- α_R\right)I_{SC}\left(e^{\frac{V_{BC}}{V_T}}-1\right) \Rightarrow C\]

Ebers Moll Model Equations For Different Modes Of Operations:

Forward Active Mode:

Base-emitter junction is forward biased (VBE is positive and greater than 1). Base-collector junction is reversed biased (VBC is negative and less than 1). We can neglect all VBC terms from the above set of equations.

\[e^{\frac{V_{BE}}{V_T}} \gg 1, e^{\frac{V_{BC}}{V_T}}\ll1\]

\[i_E = I_{SE}\left(e^{\frac{V_{BE}}{V_T}}-1\right) \] \[i_C = α_FI_{SE}\left(e^{\frac{V_{BE}}{V_T}}-1\right) = α_FI_E \]

\[i_B = (1- α_F)I_SE\left(e^{\frac{V_{BE}}{V_T}}-1\right) = (1- α_F)I_E\]

Reverse Active Mode:

Base-collector junction is forward biased (VBC is positive and greater than 1). Base-emitter junction is reversed biased (VBE is negative and less than 1). We can neglect all VBC terms from the above set of equations.

\[e^{\frac{V_{BE}}{V_T}} \ll 1, e^{\frac{V_{BC}}{V_T}}\gg1\]

\[i_E = - α_RI_{SC}\left(e^{\frac{V_{BC}}{V_T}}-1\right)\]

\[i_C = - I_{SC}\left(e^{\frac{V_{BC}}{V_T}}-1\right)\]

\[i_B = \left(1- α_R\right)I_{SC}\left(e^{\frac{V_{BC}}{V_T}}-1\right)\]

Saturation Mode:

Base-emitter junction is forward biased (VBE is positive and greater than 1). Base-collector junction is forward biased (VBC is positive and greater than 1). 

\[e^{\frac{V_{BE}}{V_T}} \gg 1, e^{\frac{V_{BC}}{V_T}}\gg1\]

\[i_E = I_{SE}*e^{\frac{V_{BE}}{V_T}} - α_R*I_{SC}e^{\frac{V_{BC}}{V_T}}\]

\[i_C = - I_{SC}*e^{\frac{V_{BC}}{V_T}} + α_FI_{SE}*e^{\frac{V_{BE}}{VT}} \]

\[i_B = \left(1- α_F\right)I_{SE}\left(e^{\frac{V_{BE}}{V_T}}-1\right) + \left(1- α_R\right)I_{SC}\left(e^{\frac{V_{BC}}{V_T}}-1\right)\]

VBE = 0.8V

VBC = 0.7V

VCE = VBC - VBE = 0.1V 

Cut-off Mode:

Base-emitter junction is reversed biased (VBE = 0). Base-collector junction is reversed biased (VBC is negative and less than 1). 

\[e^{\frac{V_{BE}}{V_T}} \equiv 1, e^{\frac{V_{BC}}{V_T}}\ll1\]

\[i_E = - α_RI_{SC}\left(e^{\frac{V_{BC}}{V_T}}-1\right) = α_RI_{SC}\]

\[i_C = I_{SC}\]

\[i_B = \left(1- α_R\right)I_{SC}\]

Important Points Learnt From This Lesson:

 Ebers Moll Model proposed a transistor model in which transistor equations can be written as a diode equation and an additional transfer ratio that is αR and αF. 

Current Division Rule:

Current Divider Rule is a renowned method of solving parallel circuits. You can solve parallel circuits using Ohm's law. But Ohm's law has a limitation. You have to know the voltage across parallel elements. This method allows you to find out the current flowing through parallel elements without knowing the voltage across it.  This procedure is derived from two very popular circuit solving laws, is Ohm's law and KCL. In this article, I am going to derive the expression of the current divider rule as well. 

Explanation:

It is only acceptable to parallel circuits where the voltage remains the same throughout the circuit. Consider a parallel circuit given below.

Figure 1: A parallel circuit

Let,

i1 = Current across R1

i2 = Current across R2

i3 = Current across R3

IT = total current across the circuit

V1 = voltage across each element

Apply KCL,

IT = i1 + i2 + i3  ….. Equation 1

From Ohm's law, i = v/R, replace "i" in Equation 1.

IT = V1/ R1 + V1/R2 +V1/R3 

IT = V1 (1/R1 + 1/R2 + 1/R3)

As you know formula for parallel resistances is

1/RT = 1/R1+1/R2+1/R3

RT = R1 || R2 || R3

IT = V1 /RT 

IT = V1/RT..... Equation 2

Now, if you want to find the current across R2, then using Ohm's law:

i2 = V1/R2 …... Equation 3

Now, solve Equation 2 and Equation 3 to get the value of i2 which is independent of V1.

IT*RT = i2*R2

Or

i2 = IT*RT/R2

Similarly, 

i1 = IT*RT/R1

i2 = IT*RT/R2

i3 = IT*RT/R3

These are the equations of current in parallel circuits which are independent of voltage. It is only applicable to parallel circuits only. These types of circuits are also called Current Divider Circuits because of the current divide among all the resistances. As you know the current adopts the least resistive path. So, the lower the resistance the higher the current flows through it.

Solved Example:

In the previous article (parallel resistance formula), I analysed and solved a parallel circuit using Ohm's law. In that case I use the following circuit.

Figure 2: Parallel circuit with a voltage source

In this tutorial, I am going to solve the same examples with the help of the current divider rule. In this example I am going to use the circuit in figure 3. Both circuits (Circuits in figure 2 and figure 3) are the same irrespective of the current and voltage sources. In the later circuit a voltage source is replaced by the equivalent current source. 

Figure 3: Parallel circuit with an equivalent current source

Example 1:

Determine total or equivalent resistance and the current flows through each resistor with the help of the current divider rule.

I solved this problem in my previous article (parallel resistance formula).

This is another way to solve this problem.

Find total resistance RT

RT = 1/R1 + 1/R2 + 1/R3

RT = 545.5 Ω

Apply CDR on each resistor.

Current through R1 is i1,

i1 = IT*RT/R1

i1 = 18*545/1000

i1 = 9.8 mA

Current through R2 is i2,

i2 = IT*RT/R2

i2 = 18*545/2000

i2 = 4.9 mA

Current through R3 is i3,

i3 = IT*RT/R3

i3 = 18*545/3000

i3 = 3.2 mA

Conclusion:

Subsequently reviewing the current divider rule, its derivation and a solved example, it is deduced that:

• This technique is useful in finding the current flows through the resistors without knowing the voltage

• The lesser the resistance the larger the current 

• It is only acceptable to parallel circuits only

The NOT Gate - Introduction & Design

 

The Inverter:

This performs the inverse operation of the buffer. It is also called the NOT gate. Output is the complement of the input. The inverter performs an inversion operation, changing one logic level to the other. 

Learning Objectives:

• Introducing AND gate implementation using

• Switches

• Diodes

• BJT

It has the same circuit symbol as that of a buffer except for the bubble present at the output side. This is the inversion bubble.

Logical Expression:

A = YC

The NOT
Input A	Output Y
0	1
1	0

Logical NOT Gate (Explain with the help of switches)

Look at the switch model, if the switch is closed (ON), the LED turns off. 

Similarly, if the switch is opened (OFF), the LED turns on. 

NOT Gate Using Universal Gates

Implementation Using Transistor Logic

When switch S1 is closed, the base-emitter junction is forward biased. Q1 is ON. No current flows from the LED. Similarly, when S1 is opened in the second case, the base-emitter junction is reversed biased. Q2 is OFF. LED turns ON in this case and hence the output is high. 

Implementation Using CMOS Logic

The Buffer Gate - Introduction &Design

 

The Buffer:

The first basic gate is a buffer. Output is the same as the input. 

Learning Objectives:

• Introducing buffer implementation using

• Switches

• Diodes

The logic symbol is the same as that of a NOT gate except the bubble. 

Logical Expression:

A = Y

The Buffer
Input A	Output Y
0	0
1	1

Logical Buffer (Explain with the help of switches)

The switch model

In practical life, we never use a switch as a buffer. The purpose of a switch model is to explain easily. Just like a switch, its purpose is to transfer the input to the output. There are so many different ways to implement the buffer logic. We will limit our study to a very basic buffer circuit. 

In digital circuit design, there are various ways to implement the buffer. 

Two inverters in series can act as a buffer:

Simple and easy task. Two inverters in series will produce the same logic as that of input. In this way the input inverses two times and the output is the same as that of the input.

Buffer with the help of an AND gate:

Consider a two-input AND gate. Connect both of its input terminals. It works as a buffer. Have a look at the schematic diagram.

Buffer with the help of an OR gate:

Consider a two-input OR gate. Connect both of its terminals. It will act as a buffer. 

Note: there is a difference between input wave and output wave amplitude. This is because every practical circuit experiences a voltage drop. The drop is due to the internal circuitry of the logic gates.

Three different ways to implement Buffer Logic

Implementation Using CMOS Logic

Two back to back inverters work as a buffer. 

The CMOS Buffer Circuit